With development in semiconductor technologies, size of semiconductor products reduces progressively. Therefore, it is an inevitable trend that the spacing between components in many semiconductor devices is highly limited. However, when the conductors are formed too close, there are adverse effects, for example, short or inductive coupling which seriously affects the performance of the semiconductor devices.
Please refer to FIGS. 1A and 1B respectively illustrating a top view and a cross-sectional view along line A-A of a typical metal-oxide-semiconductor field-effect transistor (MOSFET) structure. The MOSFET structure 1 includes a substrate 10. After several processing steps performed on the substrate 10 such as deposition, patterning and ion-implantation steps, a gate line 11, source/drain regions 12 and 13, and a gate insulating layer 14 are formed. Two contacts 121 and 131, namely source/drain electrodes, are provided on the source/drain regions 12 and 13 to be electrically connected to outer components through wires. The distances between the gate line 11 and the contacts 12 and 13 should be longer than a nominal spacing to avoid short. Since the distance is quite shorter, the accuracy for forming the gate line 11 and the source/drain regions 12 and 13 is critical. However, it is almost impossible to require that a patterning equipment has 100% alignment accuracy without any deviation in nanometer scales. Hence, while processing wafers, the equipment error should be taken into consideration, and the practical distance is not exactly the same as the nominal spacing. How to predict tolerable spacing between conductors is important to both limit the total size of the semiconductor device and avoid reducing product yield rate.
To make the prediction, operators usually collect lots of experimental data and then determine the tolerable spacing according to the experimental data in a quiet intuitive manner. At first, the standard steps of forming a plurality of source/drain regions and the source/drain contacts are carried out on a wafer. Next, moving a photomask, used for patterning and forming the polysilicon gate lines, and a lithography process are repeatedly executed through the entire wafer to transfer the pattern to a photoresist layer provided on a polysilicon layer which will be patterned to from the polysilicon gate lines later. In this step, the photomask is progressively shifted from predetermined positions to various deviated positions towards or away from the source/drain contacts. In other words, various little deviation is intentionally introduced in this step. For example, first deviation is introduced in a first lithography process, second deviation is introduced in a second lithography process and so on. After the formation of the gate lines 11 with different deviations, an electron beam inspection (EBI) system capable of detecting electrical defects such as a short or a leakage defect by detecting bright voltage contrast (BVC) is utilized to find failure count for each deviation.
Please refer to FIG. 2 illustrating a plot of failure count vs. deviation of the photomask. It is found that in a safe window, the failure count (amount) is within an acceptable range. Hence, the operator should control the deviation within the safe window in subsequent normal production. It is to be noted that the plot is not symmetrical about zero deviation due to alignment error. Hence, it is possible that the optimum position of the photomask is not the predetermined position. The acceptable position or the optimum position of the photomask, which may be deviated from the predetermined position, is thus obtained from the determined safe windows.
However, the safe window is determined by operators by visual analysis without scientific base. Different operators may obtain different prediction results. Furthermore, the prediction result cannot be scaled up or down even for the same patterning equipment. The inspection system has to scan all the die area. For example, 1 MB static random access memory (SRAM) density per die means total 1,048,576 (1,024*1,024) scan counts per die. It is really time-consuming for the inspection, and the entire process including determining the safe window to adjust position parameters of the photomask is uncompetitive. Hence, there is a need of providing an improved method for predicting the tolerable spacing between conductors in semiconductor device to overcome the problems encountered in the prior art.